The global semiconductor map is rewriting its coordinates. Between September 27 and October 1, 2026, a series of capital deployments and yield adjustments showed that sovereign silicon is no longer a policy talking point—it is a physical construction project.
While TSMC pushes the pricing envelope of leading-edge logic to historic highs, India is aggressively building out the physical infrastructure required to anchor its own chip manufacturing ambitions.
India’s Hard-Hat Phase: Fabs, OSAT, and Semicon 2.0
The Union Cabinet's approval of "Semicon 2.0" marks a structural shift in state support. With an allocated outlay of ₹1,27,500 crore ($13.5 billion), the updated policy expands government incentives beyond foundational fabrication units. The capital now targets the entire supply chain: manufacturing equipment, raw materials, specialized design tools, and advanced packaging.
Under the initial Semicon India programme, the government approved 12 semiconductor manufacturing projects representing a cumulative investment exceeding ₹1.64 lakh crore. The transition from blueprint to operational cleanroom is already visible. Three projects—Micron, Kaynes, and CG Semi—have commenced commercial production, establishing early momentum in assembly and testing.
The heavy industrial lifting is concentrated in two major hubs:
- Dholera, Gujarat: Tata Electronics, in partnership with Taiwan’s PSMC, is constructing India’s first commercial wafer fab. This ₹91,526 crore facility targets a capacity of 50,000 wafer starts per month (WSPM), with first silicon expected to roll out between 2026 and 2027.
- Morigaon and Sanand: Packaging infrastructure is scaling in parallel. Tata is building a ₹27,000 crore OSAT facility in Morigaon, Assam, while Micron Technology is constructing its ₹22,516 crore ATMP/OSAT plant in Sanand, Gujarat.
This rapid infrastructure deployment is detailed further in our analysis of the India Semiconductor Mission's OSAT facilities, which highlights how regional supply chains are adapting to these massive capital inflows. For a deeper breakdown of the construction timelines, see our report on the Dholera and Sanand buildouts.
India Semiconductor Capital Allocations (Selected Projects)
┌──────────────────────────────────────┬───────────────────────┐
│ Project / Initiative │ Investment Value │
├──────────────────────────────────────┼───────────────────────┤
│ Semicon 2.0 State Outlay │ ₹1,27,500 crore │
│ Tata-PSMC Dholera Wafer Fab │ ₹91,526 crore │
│ Tata Morigaon OSAT Facility │ ₹27,000 crore │
│ Micron Sanand ATMP/OSAT Facility │ ₹22,516 crore │
└──────────────────────────────────────┴───────────────────────┘
Upstream suppliers are positioning themselves near these hubs. Applied Materials has committed $5 billion over ten years to scale up Indian research, workforce training, and supply-chain logistics. Simultaneously, homegrown edge AI chip startups are securing early-stage capital. Indian edge AI design firms raised $17 million in 2026—a steep climb from the $4.27 million raised in 2022. This design surge is supported by 105 startups gaining subsidized access to government-backed EDA tools, a pipeline bolstered by the country's broader deep tech funding initiatives.
TSMC’s N2 Premium and the Logic Supply Squeeze
As India builds its 28nm and 40nm foundations, the leading edge of global chip manufacturing is seeing unprecedented pricing pressure. On September 29, 2026, reports confirmed that TSMC revised its 2-nanometer (N2) production targets upward by 20%.
The foundry giant now aims to produce 120,000 wafers per month by the end of 2026. This aggressive ramp-up comes with a steep premium. Industry analysts estimate that a single N2 wafer will command a price of $30,000.
The high cost reflects the complexity of transitioning to backside power delivery and nanosheet transistor architectures. Hyperscalers and premium smartphone designers are absorbing these costs to secure performance gains, leaving trailing-edge nodes to compete on volume and regional supply security.
The DRAM Pricing Reversal: HBM Alters Silicon Economics
On September 30, 2026, market analyses highlighted a historic pricing anomaly: DRAM now generates more selling value per square millimeter of silicon than TSMC’s leading-edge logic wafers.
This reversal is driven entirely by the structural demands of High-Bandwidth Memory (HBM). HBM architectures require approximately three times the physical wafer area of standard DDR5 memory to achieve equivalent bit output. This massive silicon footprint has created a global wafer supply bottleneck.
Silicon Value Comparison (Relative Yield Value per mm²)
┌──────────────────────────────────────────────────────────────┐
│ Leading-Edge Logic (TSMC N3/N2) │
│ ▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓ │
├──────────────────────────────────────────────────────────────┤
│ High-Bandwidth Memory (HBM Stacked Silicon) │
│ ▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓ │
└──────────────────────────────────────────────────────────────┘
The financial impact of this dynamic is clear in Micron Technology’s fiscal Q4 2026 earnings, released on September 30. Micron reported projected DRAM sales of $38.3 billion—a 330% year-over-year increase—bringing its total projected sales to $50.9 billion.
Intel’s Consolidation and SK Hynix’s US Gambit
While memory manufacturers ride the HBM wave, the foundry sector remains highly volatile. Intel stock faced a 7% pullback to open near $118.70 on September 28, 2026. This correction followed a massive 40% rally earlier in the month, which was driven by optimistic CPU demand forecasts and reports of SK Hynix exploring US-based memory packaging options using Intel’s domestic foundry capacity.
Intel's capacity utilization strategy highlights the friction of building advanced packaging ecosystems outside of Asia. While governments globally subsidize fab construction, the actual yield, packaging availability, and raw wafer supply remain concentrated in tight corridors. For India, the immediate challenge is ensuring that the Dholera fab and the Sanand and Morigaon packaging units mature fast enough to capture local demand before global macroeconomic shifts alter capital flows.
